2. Technical Field
The present invention relates to data processing systems, and more particularly to a method and apparatus for checking integrated circuit chips having programmable signal lines.
3. Background Art
U.S. Pat. No. 4,176,258 of Daniel Jackson, granted on Nov. 27, 1979, discloses a method and circuit for checking integrated circuit chips commonly known as functional redundancy checking (FRC). The basic principle is to have a master-checker pair of identical chips connected in parallel. Only one chip, the master, actually drives its outputs. The other chip, the checker, inhibits its outputs. There is checking circuitry on each identical chip. This checking circuitry is activated only on the chip designated as the checker, thus making it possible to fabricate the chips identically, with the advantage of only one part number and no external error checking circuitry. When activated, the checking circuitry compares the value on the output pins of the two chips. If the compared values differ, then an error is flagged.
In the prior FRC scheme, the time during which the comparison take place is not variable and is usually some fixed time after an output pin should have been driven. This is possible because the data-processing logic in the chip drives each output pin at a fixed time in the processor cycle. This also implies a maximum settling time for the pin value. If the external load is such that the output pin does not settle to its expected value before the checking circuitry makes its comparison, then the checking circuit will use the wrong value and flag a false error (or miss a real one).
The above-identified U.S. Pat. No. 4,785,428, discloses a memory control unit (MCU) that will generate any pattern of control signal timings to provide a range of timing controls for dynamic random access memory (DRAM) operations.
The transitions on the pins are user-programmable and do not occur at a fixed time in the processor cycle. In fact, the pin may even change twice in a cycle. An FRC logic must take this into account. Also, the external loads may cause settling times to vary so that the point of comparison of the output value has to be determined in a more complex manner.
It is therefore an object of the present invention to provide a redundant checking logic for integrated circuit chips the outputs of which are time-variant programmable.